Cloud native EDA tools & pre-optimized hardware platforms
Synopsys Silicon WorkBench (SiWB) is a powerful, hierarchical layout visualization and analysis tool. It allows viewing and editing GDSII and OASIS® layouts from small IP blocks to full chip databases.
Gigabytes of data can be loaded within minutes. Fast zooming and panning ease exploration and analysis of the largest layout patterns. Layout centric S-Litho, S-Metro, and TCAD applications are supported through a dedicated user interface to simplify the handling of layout clips.
Synopsys Silicon WorkBench provides high speed, high-capacity layout viewing and editing capabilities for GDS2, OASIS, and LEF/DEF files with low memory overhead. It covers various modes for merging layout of mixed format, compares layouts, cells, and generates difference reports.
Besides flexible user and site-level customization options, Synopsys Silicon WorkBench provides application specific environments and users interfaces supporting the following Synopsys products:
Synopsys Silicon WorkBench can be used as a cockpit for running rigorous lithography simulations in the background and visualizing results within the layout context. It enables distributed processing for multiple layout clips and provides the infrastructure for resist model calibration and well a training environment for machine learning models.
Synopsys Silicon WorkBench supports layout operations in combination with Synopsys S-Metro, a comprehensive solution for CD SEM metrology data visualization and analysis. SEM images can be overlayed with the corresponding layout clip to identify measurement locations, to extract image contours, and display analysis results.
Within the Synopsys Silicon WorkBench GUI users can conveniently add special mark-ups to a standard layout file to easily drive layout-driven processing simulations with TCAD tools, such as Sentaurus Process, Process Explorer, and Sentaurus Interconnect. Specifically, users can define 1D, 2D, and 3D TCAD simulation domains, as well as markers for TCAD-specific layout parametrizations.