Tower Semiconductor PDK-Based QPSK Transceiver PIC Design for High-Speed Data Center Interconnects

Tools Used: OptSim Circuit, OptoDesigner

Introduction

Inter- and intra-data center traffic have grown by leaps and bounds over the last decade. While advanced modulation formats help address the distance and capacity limitations of data center interconnects, photonic integration remains a key to economic success because of the inherent benefits it offers, such as energy efficiency, reliability, and scalability. The role of photonic design automation (PDA) tools is as indispensable to photonic integration as was (and still is) the role of electronic design automation (EDA) tools to the fruition of Moore’s law for CMOS over the last 50 years. The Synopsys tools fit naturally into the foundry process design kit (PDK)-driven photonic integrated circuits (PIC) design flow [1].

This application note demonstrates a complete PIC design using OptSim Circuit and OptoDesigner. This example starts with an idea or concept and flows to circuit simulation, design rule checks (DRCs), layout vs. schematic (LVS) check, GDS II layout generation, and analysis of foundry process variations on yield. The study involves design of a high-speed quadrature phase-shift keying (QPSK) transceiver PIC using the Tower Semiconductor silicon process (PH18) PDK [2].

Concept: QPSK Transmitter

Conceptually, a QPSK transmitter (I-Q modulator) is made up of in-phase and quadrature modulated components as shown in Figure 1.

The laser output is split into two arms, each phase-modulated with different high-speed data streams as BPSK (binary phase shift keying), and then combined in quadrature, essentially doubling data carrying capacity over a single wavelength compared to that of a legacy intensity modulated binary transmitter. The component is scalable in the sense that multiple I-Q modulators with appropriate bias can be reused to support higher-order modulation formats (such as 16-QAM, 64-QAM, …) to provide higher spectral efficiency. 

Schematic Entry, Generation of Layout, and Design Rule Checks (DRC)

Figure 2 shows an OptSim Circuit schematic of the QPSK transmitter in Figure 1 using the Tower Semiconductor silicon process (PH18) PDK. The connections between the PDK elements are “hard” connections. Hard connections are parametric PDK elements providing optical connectivity between the adjacent functional blocks (also represented by PDK) of a PIC. 

The OptSim Circuit GUI launches OptoDesigner and loads the script for the PIC schematic. Figure 3 shows the corresponding layout from OptoDesigner.

Concept: QPSK Receiver

The operating principle of a QPSK receiver is shown in Figure 4.

The received optical signal is mixed with a local oscillator using an optical 90-degree hybrid coupler for homodyne detection at the balanced photodetectors. Just like the I-Q modulator, the receiver is also scalable to support polarization diversity and higher levels of modulation.

Schematic Entry, Generation of Layout, and Design Rule Checks (DRC)

Figure 5 shows an OptSim Circuit schematic of the QPSK receiver (Figure 4) using Tower Semiconductor silicon process (PH18) active and passive PDK elements. The connections between the PDK elements are “hard” connections. 

Photonic connectivity is realized with bends, tapers and couplers. The shown connectivity has incoming modulated and local oscillator signals mix from the opposite ends of the 90-degree hybrid resulting in a compact layout in OptoDesigner.

As before, the OptSim Circuit GUI launches OptoDesigner and loads a script for the PIC schematic. Figure 6 shows the corresponding layout in OptoDesigner.

Testing the QPSK Transceiver PIC Performance

Figure 7 shows an OptSim Circuit test setup for a Tower Semiconductor PDK-based high-speed, photonic QPSK transceiver chip. 

The two blocks in the middle with red dotted lines around them are QPSK transmitter and receiver PICs. On the left of the design area, there’s an off-chip laser emitting light at 1550nm, a standard telecom C-band wavelength. Two decorrelated data sources with NRZ drivers and low pass filters provide push-pull RF drives at 32-Gbd/s speed to the modulators, while bias signals choose the bias points for the modulators.

The transmitter and receiver PICs are connected back to back. Another off-chip laser at the receiver serves as a local oscillator. To provide homodyne detection, the laser wavelength is identical to that of the received signal.

On the right of the receiver PIC, the balanced post-detection electronics extract in-phase and quadrature components of the received QPSK signal. The blocks in yellow are measurement components for visualization of signals, spectra, eye diagrams, BER, etc.

Figure 8 shows waveforms at the transmitter PIC.

The plot at the top left shows the modulated optical signal at the output of the transmitter. Since QPSK is phase modulation, amplitude is constant while phase transitions are shown. The lower left plot shows the optical spectrum of the QPSK-modulated signal at the transmitter output. On the right is QPSK constellation symmetric around the origin observed at the output of the transmitter PIC.

Figure 9 shows waveforms at the receiver PIC.

On the left are the received electrical signals for the in-phase (top) and quadrature (bottom) components of the signal. High and low levels of the electrical signal show noise due to the photodetection process and the transimpedance amplifiers at the receiver. As the eye diagrams on the right show, the performance of the transceiver PIC based on Tower Semiconductor PDK is excellent at 32-GBps symbol rate (which is 64-Gbps over a single wavelength).

Evaluating Impact of Foundry Process Variations

There are a number of papers that discuss the impact of receiver imperfections in QPSK systems [3-4].

The current study has a Gaussian fluctuation introduced around the mean value of the phase-shifter length for the in-phase component at the receiver. A parameter scan is setup for 100 Monte Carlo runs. Bit-error-rate (BER) values are collected for different amounts of deviations and are plotted in Figure 10. 

The sources for receiver imperfections could lie in component tolerancing and/or fabrication process variations. As this application note illustrates, OptSim Circuit is an excellent platform to study such effects – because of deterministic variations as well as stochastic variations. Such analyses can help estimate performance bounds and predict yield as evident from Figure 10. 

Layout-Versus-Schematic (LVS)

The Layout-Versus-Schematic (LVS) check is an important stage before generating the final GDS II output. The LVS comparison is a software check to ensure that the OptoDesigner layout is identical to the OptSim Circuit schematic. The previous example used hard connections and there were no changes done at the layout level, so the LVS is not crucial for this specific case. However, for the sake of illustrating the full flow, we perform an LVS check. A runset file comprises of spice netlists from OptSim Circuit schematic and from an OptoDesigner-annotated GDS. Synopsys IC Validator [5] uses the runset file and compares the two netlists. Figure 11 shows a “Pass” output from IC Validator.

Packaging

Before we place the transceiver PIC in a die, we use OptoDesigner to add electrical pads and vias for electrical routing as shown in Fig. 12. 

For layout compactness, several levels of metals are used in electrical routing shown in Figure. 12.

Figure 13 shows GDS II view of the transceiver PIC (top) and the view when the PIC is placed in a Tower Semiconductor die (bottom).