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| User Papers and Presentations |
| A1 - Early RTL Exploration and Synthesis |
Exploration on CPU/GPU Designs with DC Explorer (Technical Committee Award Honorable Mention)
Author(s): Choukri Saidi, Sébastien Peurichard - STMicroelectronics |
|
| A2 - Testbench Qualification |
Certitude Advanced Tips
Author(s): Jean-François Vizier - Dialog Semiconductor |
|
Qualification of Complex Systems Multi-Purpose Processor Array
Author(s): Jehan-Philippe Barbiero - Kalray |
|
Verification Quality Improvement Using Synopsys Certitude C/C++
Author(s): Mikaël Genay - STMicroelectronics, Ali Abbara, Florian Letombe, Julien Torrès - Synopsys |
|
| A3 - Physical Design Implementation |
Engineering Change Order (3rd Place - Best Paper)
Author(s): Didier Gueze, Jyoti Kumar, Sandesh Jain, Swati Narang - STMicroelectronics |
|
Optimizing Standard Cell Pin Accessibility in 14nmFDSOI with Synopsys Pin Access Checker
Author(s): Olivier Aupoix, Somya Agarwal, Nour Ben Salem - STMicroelectronics, Alain Boyer - Synopsys |
|
| A4 - Design for Test and ATPG |
Configurable On Chip Clocking Controller Clock Bit Chain Length to Minimize Test Compression OCC Dedicated Scan Access at SOC Level
Author(s): Christophe Eychenne - STMicroelectronics |
|
Generating Pattern to Debug Chain Segments in DFTMAX X-tolerant Mode
Author(s): Matthieu Sautier – STMicroelectronics, Salvatore Talluto - Synopsys |
|
| A6 - Mixed-Signal Verification I |
Simulating Voltage Scaling For Real Applications
Author(s): Franck Gardic, Robin Wilson, Anne Lombardot - STMicroelectronics, Philippe Brahic - Synopsys |
|
| B1 - Advanced Synthesis and Formal Verification Techniques |
Implementation of a Wireless DSP in 40nm Using DC Graphical
Author(s): Peter Debacker, Veerle Derudder, Ilse Vos, Andy Dewilde, Antoine Dejonghe - IMEC |
|
Using Synopsys Physical Guidance Flow with Design Compiler Graphical and IC Compiler for Achieving Maximum Performance and Minimum Leakage Goals for LEON3 Core-based Designs
Author(s): Alexander Korolkov, Igor Orlovsky, Andrey Veitsel - Topcon Positioning Systems, Russia, Jan Andersson - Aeroflex Gaisler, Feodor Merkelov, Dmitry Radchenko - Synopsys |
|
| B2 - Adopting UVM Methodology and Next Generation VIPs |
Easier UVM: Guidelines and Automatic Code Generation to Accelerate UVM Adoption
Author(s): John Aynsley, Dr. Christoph Sühnel and Dr. David Long - Doulos |
|
Using Synopsys CSI2 VIP for IP-Level Verification
Author(s): Jose Mangione, Noreddine Ben El Kardadi, Zineb Sakout Andaloussi - STMicroelectronics, Xavier Mathes - Synopsys |
|
| B3 - In-design Physical Closure and Signoff Accuracy |
Improving STA Productivity at 32nm/28nmFDSOI and Below (1st Place - Best Paper)
Author(s): Sébastien Marchal - STMicroelectronics |
|
In-Design Automatic DRC Repair Flow Using IC Compiler and IC Validator
Author(s): Stephane Pautou - STMicroelectronics, Alain Boyer - Synopsys |
|
| B4 - Improving Test Quality and Yield |
Better Faster Stronger Diagnostic Approach with Synopsys’ Yield Explorer
Author(s): Jean-Marc Denollet, Thomas Droniou - STMicroelectronics, Christophe Suzor - Synopsys |
|
Physical Data Loading to Improve Diagnosis Accuracy (2nd Place - Best Paper)
Author(s): Nelly Feldman, Vincent Robert – STMicroelectronics, Christophe Suzor, Salvatore Talluto - Synopsys |
|
R&D Q&A Session - Volume Diagnostics for Accelerated Yield Learning in Advanced Technology Nodes
Author(s): Christophe Suzor - Synopsys |
|
| B6 - Custom Design Methodology and Signal Integrity |
Adding a Metal Fringe Capacitance to an iPDK
Author(s): Alain Vigne - Blinksight |
|
New Advanced Methodology for Parasitic Extraction Aimed at Post Layout Analysis in BCD Technologies
Author(s): Davide Cavalli, Luciana Paciaroni - STMicroelectronics, Claudio Rallo - Synopsys |
|
| B7 - Galaxy Custom Router |
Hands-on Galaxy Custom Router Workshop with Competition and Prize Draw
Author(s): Fouad Bissane - Synopsys |
|
| C1 - Low-Power Static Checking |
New Generation of Low-power Static Checker
Author(s): Irène Serre, Pascal Blanc - STMicroelectronics |
|
| C2 - Hardware-based Verification |
Accelerating the Validation of a Secure ROM with ZeBu
Author(s): Gherardo Gorni, Simone Borri – Abilis Systems |
|
| C3 - IC Compiler II |
IC Compiler II: A Fast Methodology to a Good Hierarchical Floorplan
Author(s): Pascal Teissier – STMicroelectronics, Gaspard Thaller - Synopsys |
|
New Breakthrough in Physical Design Productivity
Author(s): Claire Mauduit, Johann Meleard - STMicroelectronics, Hervé Raffard - Synopsys |
|
| C4 - SMS & SHS Technologies for IEEE 1500 SoC |
STAR Hierarchical System (SHS) Architecture Implementation in Full IEEE1500 SoC (1st Place - Best Paper, Technical Committee Award)
Author(s): Cédric Escallier - STMicroelectronics |
|
| C6 - Mixed-Signal Verification II |
Analog-on-top AMS Verification - a Practical Approach
Author(s): Jonathan Bradford, Gernot Koch - Micronas |
|
| Keynote |
Designing Change Through Innovation and Collaboration
Author(s): John Chilton, Senior Vice President and General Manager, Coverity, Synopsys Inc. |
