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| User Papers and Presentations |
| A1 - Clock Domain Crossing Checking |
SDSAC - Self-Driven Synchro Analyser and CDChecker. A GCA Based Method for CDC and Synchronizers Analyser
Author(s): Fabio Crippa, Antonio Griseta - STMicroelectronics |
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| A2 - Testbench Qualification and Formal Verification |
Formal Qualification of Functional and Connectivity Formal Verification Environments at SoC Level Using Synopsys Certitude
Author(s): Massimo Zendri - STMicroelectronics |
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| A3 - IC Compiler II |
ICC/ICC II Physical Implementation Comparison of a GPU Partition (1st Place - Best Paper)
Author(s): Anna Asquini, Corine Pulvermuller - STMicroelectronics; Vincent Sornette - Synopsys |
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| A4 - Design for Test and ATPG |
MAXtestbench - A Technology to Manage STIL Pattern Qualification in Complex SoC Verification Environment
Author(s): Guillaume Costrel de Corainville, Mickael Broutin - STMicroelectronics |
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TetraMax Power Aware ATPG Capabilities on a Production Chip, a User Experience (Technical Committee Award Honorable Mention)
Author(s): Julien Pouget, Joseph Alan, Guillaume Megrette - Ericsson; Philippe Rossant - Synopsys |
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| A5 - Custom Design |
FDSOI - An Interoperable Technology
Author(s): Gilles Namur - STMicroelectronics |
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| A6 - AMS Verification |
Automated Flow for High DC Current Verification
Author(s): David Turgis, Faress Tissafi Drissi - STMicroelectronics |
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Extending New Verification Techniques to Mixed-Signal SoCs with VCS AMS
Author(s): Pierluigi Daglio, Mauro Scandiuzzo, Alessandro Valerio - STMicroelectronics; Helene Thibieroz, Massimo Prando, Carlo Borromeo - Synopsys |
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Simulation & Silicon Verification of Adaptive Voltage Scaling for Real Applications
Author(s): Darayus Adil Patel, Robin Wilson, Franck Gardic, Sylvie Naudet - STMicroelectronics; Arnaud Virazel, Patrick Girard - LIRMM; Philippe Brahic - Synopsys |
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| B1 - Advanced Low Power Synthesis Techniques for Energy Management |
Advanced Synthesis Technique Using Target Library Subset (Technical Committee Award)
Author(s): Laurent Besson - STMicroelectronics |
|
Minimum Energy Design for Sub-threshold Wireless Sensor Nodes
Author(s): Seng Oon Toh, James Myers - ARM |
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Succeeding in Implementing a Low-Power SoC with Power Islands
Author(s): Lucille Engels, Bruno Bailly, Andréa Bonzo, Frédéric Bunoz, Guillaume Cogniard, Faustine Coguen, Sébastien Gaubert, Grégoire Gimenez, Rémi Malaquin, Hai Yu - Dolphin Integration |
|
| B2 - Adopting UVM Methodology I |
A Comprehensive UVM Verification Environment for MPEG Transport-Stream Processing
Author(s): Filippo Borlenghi, Simone Borri, Gherardo Gorni - ALi Europe |
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Adopting UVM Methodology for IP Level Verification
Author(s): Giovanni Auditore, Francesco Rua' - STMicroelectronics |
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| B3 - Physical Implementation and Design Closure |
A53 Core Optimization to Achieve Performances
Author(s): Calogero Timineri, Julien Buvat, Julien Guillemain, Sébastien Peurichard - STMicroelectronics |
|
In-Design Metal Fill Insertion for Faster Timing Convergence (2nd Place - Best Paper)
Author(s): Raphael Gras, Ahmed Oumina - STMicroelectronics; Emmanuel Pluchart - Synopsys |
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| B4 - Improving Test Quality and Yield |
High-end Test Compression Methodology for Low Pin Count Products in Secured Environment
Author(s): Caroline Carin, Arnaud Donné - STMicroelectronics |
|
Using TetraMAX Diagnosis for Silicon Debug and Pattern Masking Delivery, on a Complex 28nm FDSOI SoC, Embedding DFTMAX with Serializer Compression Technology
Author(s): Rachid Idrissi, Mohamedarif Alarakhia - STMicroelectronics; Philippe Rossant - Synopsys |
|
| B6 - Parasitic Extraction and Reliability Analysis |
Automatic Feed-through Parasitic Extraction for Memory Compiler Spice Simulations
Author(s): Fabien Leroy - ARM |
|
EM/IR Verification of a 14FDSOI Video DAC Using CustomSim-RA
Author(s): Alejandro Chimeno, Francois Lemery, Véronique Bessodes, Nicolas Pelloux - STMicroelectronics |
|
Reliability Checks on Signal and Supply Net Topologies of Mixed Analog and Digital and Power ICs
Author(s): Marco Raimondi, Francesco Adduci, Paolo Valente - STMicroelectronics; Claudio Rallo - Synopsys |
|
| C1 - Advanced Physical Synthesis and Design Exploration |
Standard Cells Placement Exchange Between Design Compiler Graphical and IC Compiler (3rd Place - Best Paper)
Author(s): Jean-Marc Calvez, Sébastien Peurichard, Choukri Saidi - STMicroelectronics |
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| C2 - Adopting UVM Methodology II |
Migrating to UVM Verification Environment for Imaging Applications
Author(s): Kevin Rowley, Boris Rizov - Apical Imaging |
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| C3 - Characterization and Sign-off |
CCS Noise Library Generation and Checking
Author(s): Benoît Lasbouygues - Atmel Corporation |
