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| User Papers and Presentations |
| A1 - Advanced Design Methodology |
In-design Track Fill in IC Compiler II (Technical Committee Award Honorable Mention)
Author(s): Didier Gueze - STMicroelectronics |
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Merging ST Low Uncertainty Clock Tree with ICC2 Multi-Source Clock Tree Methodology for Better QoR
Author(s): Pierpaolo De Laurentiis, Alberto Ferrara - STMicroelectronics; Francesco Lannutti, Aurelio Monti - Synopsys |
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RM Flow Customization Experience
Author(s): Giacomo Cappellin - STMicroelectronics |
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| A2 - Adopting UVM Methodology |
Yet Another Memory Manager (YAMM)
Author(s): Ionut Tolea, Andrei Vintila - AMIQ Consulting SRL |
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| A3 - Power Estimation and Analysis |
Using Siloti for Early and Accurate Power Estimation
Author(s): Cyril Chevalier, Audrey Le-Clercq - STMicroelectronics |
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| A4 - Design for Test and Compression |
DFTMAX-Ultra to Enable High Test Coverage for an Ultra-Low Pin Count Design Embedding a Test Mode Controller
Author(s): Mohrad Mammasse - STMicroelectronics |
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Run Time Reductions for Fast DFT Development
Author(s): Fabien Chiantia, Cedric Escallier - STMicroelectronics |
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Using DFTMAX Shared IO on a Complex ASIC, a User Experience
Author(s): Benoit Leconte - Atos/Bull |
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| A6 - AMS Simulation and Debug |
A GVI SystemVerilog Nettype Ready for Mixed-signal Simulations
Author(s): Sebastien Cliquennois, Francois Ravatin - STMicroelectronics |
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PageFlash Memory Verification: Co-simulation Methodology for Early Debug and Extensive Coverage Based on VCS AMS (CustomSim-VCS)
Author(s): Enrico Castaldo - STMicroelectronics |
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| B1 - Congestion and Area |
Improve Predictability and Routability by Anticipating CTS Routing Topology
Author(s): Luc Sponga, Corine Pulvermuller - STMicroelectronics; Sébastien Paquet - Synopsys |
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Reduce Chip Area in a High Routing Congested ARM CortexM3 Design
Author(s): Jens Mayer - Micronas New Technologies |
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Use of Physical Feedthroughs in a Mixed Signal Design with IC Compiler and IC Compiler II
Author(s): Christelle Leherpeur - STMicroelectronics |
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| B2 - RTL Checks and Restructuring |
Conclusive Formal Verification of Clock Domain Crossings using SpyGlass-CDC (Technical Committee Award)
Author(s): Mejid Kebaili, Jean-Christophe Brignone - STMicroelectronics; Guillaume Plassan, Jean-Philippe Binois - Synopsys |
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RTL Restructuring with Massive Feedthrough to Allow Channel-less Implementation
Author(s): Yann Bonhomme - STMicroelectronics |
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SpyGlass Based DFT Checks
Author(s): Philippe Debaud - STMicroelectronics |
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| B3 - Sign-off |
Improved Turnaround Time and Performance using Parametric OCV in 28nm FD-SOI Technology (1st Place - Best Paper)
Author(s): Tarun Chawla - STMicroelectronics |
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Noise/Power Sign-off ECO Methodology and New Advanced Features
Author(s): Olivier Corvoisier - Atos/Bull; Patrick Belmond - Synopsys |
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| B4 - Physical Aware Design for Test and Safety for ISO 26262 |
Alternative DFT Solutions to Cope with Physical Congestion
Author(s): Matthieu Sautier, Mohamedarif Alarakhia, Rachid Idrissi - STMicroelectronics |
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Using DFTMAX with both Asynchronous and Synchronous On Chip Clock Controllers (OCC), in a Highly Constrained Environment, a User Experience
Author(s): Maxime Peycelon - Thales; Philippe Rossant - Synopsys |
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| B5 - SoC Prototyping |
3D Stacked Sensor Prototyping using HAPS-70: Maximizing HAPS Utilization by using a Multi Design Approach
Author(s): Hubert Deborgies - STMicroelectronics |
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| B6 - Advanced Analog Verification Flows |
Innovative Propagation Methodology for Diodes and Clamps by Using TCL-CCK Advanced Capabilities in Synopsys Circuit Check
Author(s): Luca Togni, Mauro Fragnoli, Paolo Ghigini, Salvatore Santapa, Pierluigi Daglio, Alessandro Valerio - STMicroelectronics; Carlo Borromeo - Synopsys |
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Insights about Ageing Simulation with Fast SPICE CustomSim (XA) Memory Applications at STMicroelectronics
Author(s): Florian Cacho, Atul Bhargava, Radhika Gupta, Dorfy Rao - STMicroelectronics |
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System Level Verification with CustomSim PCM (Phase Change Memory) Built-in Cell (2nd Place - Best Paper)
Author(s): Chantal Auricchio, Alberto Balzarotti, Massimo Borghi, Alessandro Valerio - STMicroelectronics; Tien Pham, Claudio Rallo - Synopsys |
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| C1 - Design Planning with IC Compiler II |
28nm FD-SOI FlipChip Design with IC Compiler II
Author(s): Raphael Theveniau - STMicroelectronics; Alain Boyer - Synopsys |
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| C2 - Verification for Safety |
A New Methodology for Automotive Design Robustness to Defects, Using Certitude at RTL and Gate Netlist Level
Author(s): Hubert Marcel, Aymeric Leroy - STMicroelectronics |
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| C3 - Advanced Equivalence Checking Flows |
Optimizing Finite State Machine Functional ECOs with Formality Ultra
Author(s): Andrea Di Ruzza - STMicroelectronics |
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| C4 - SoC Test ATPG, Diagnostic and Repair for Yield |
Fast Yield Ramp by Correlating Failed Test Diagnostics and Fab-related Design Hotspots (3rd Place - Best Paper)
Author(s): Nelly Feldman - STMicroelectronics; Christophe Suzor, Salvatore Talluto - Synopsys |
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Path Delay HOLD Checking and Diagnosis
Author(s): Nicolas Falcot, Cédric Escallier - STMicroelectronics |
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| C5 - IP & Complex Subsystem Prototyping |
FPGA Prototyping of a Complete System-on-Chip with the HAPS-DX7
Author(s): Sandro-Diego Wölfle - Hyperstone GmbH |
