Astrileux and Synopsys demonstrate the performance of new multilayer mask blank materials on photoresists and wafers in next generation lithography. We present new mask materials that exhibit superior on-wafer imaging properties, and improved performance in critical lithography parameters such as dose, critical dimensions (CD), normalized image log slop (NILS) and depth of focus (DOF). Specifically we examine the optimization of material and architecture properties of coatings, and demonstrate how their reflectivity profiles influence the CDs obtained for different pitches, illumination conditions and complex numerical aperture systems. Consequently we can quantify direct improvements in CD as a result of new mask materials and their architectures.

Presenter

Supriya L. Jaiswal

Astrileux Corp. (United States)

Various mask PORs based on ArF PSM and EUV mask are analyzed using Monte-Carlo simulation and EB Mask simulator through empirical method. Energy intensity distribution (EID) and point spread function (PSF) are evaluated, which are determined by electron beam energy and substrate properties. We analyze the correlation of EID, patterning feature and CD of mask process to be optimized for high-grade products. From EB mask simulation, we study the characteristics of PSF generated by electron beam scattering according to changes in energy and material. PSF Gaussian parameter fitting is applied to obtain optimum resist parameters. As a result, we find optimum process parameters that are consistent with the actual process. Using accurate model in simulation, we evaluate the mask error of various mask processes and study the correlation according to different mask conditions. For application and verification, we use complex patterns such as ILT and monitor CD error changes according to blank material (MoSi, EUV), CAR properties (P-type, N-type, sensitivity), and data format (VSB, MALY). Finally, we predict mask error impacts on the ArF process for PSM and EUV lithography.

In this paper, we demonstrate the efficient use of contours extracted from mask SEM images to characterize features with respect to placement, pattern fidelity, and uniformity. Absorber defects, can be automatically detected, and categorized. To assess the probability of mask defect printing, we show how an extracted mask image contour can be used as input for a rigorous lithography 3D resist process simulation to quickly estimate the severity and potential printing behavior in resist of a defect through dose and focus. Simulation results are being validated by wafer data. The results of this work could provide guidelines for the mask making process and mask inspection.

Metalenses are flat lenses made from thin films that operate using phase effects to manipulate light. Metalenses are used in visible and infrared ranges for applications ranging from infrared facial recognition for cell phones to telescopic imaging of astronomic objects. Understanding metalens performance response to a process variation range accepted by manufacturers can lead to more robust manufacturing processes. This study will simulate metalenses that have been optimized to a specific manufacturing process. Process models will be used to vary process conditions such as etch time, photoresist thickness, or patterned material thickness. The resulting metalenses will be simulated using electromagnetic field solvers to generate lens metrics such as focal efficiency or power attenuation. The resulting simulation data can be used to improve metalens designs and manufacturing processes.

As we enter the curvilinear mask and multi-beam writer era, a new fracture engine is needed. In this presentation we introduce an innovative fracture engine called SmartFracture. The new engine can handle the Bezier curves natively, which enables high accuracy and smaller output file size. We will explore the characteristics of Bezier curve data representation and full chip results with the new engine.

This paper presents a system for performing mask error correction on both Manhattan (including 45-degree and rotated-Manhattan) and curvilinear shapes. On the Manhattan shapes, the correction may move segments (dissected edges), and on the curvilinear shapes, the correction may move vertices. The segment movement preserves the Manhattan style of the original shapes. Optionally, the vertex movement may be applied on the Manhattan shapes and the corrected results change to be in the curvilinear style. The results of mask error correction on the post-OPC mask of a large logic layout will be reported. Dissection and target-point placement work differently between Manhattan and curvilinear shapes. We will analyze the quality and demonstrate optimization of the mask error correction strategies for input mask data consisting of both Manhattan and curvilinear shapes.

This paper reports a pre-processor that simplifies curvilinear figures coming at multiple scales to reduce the degrees of freedom. The downstream consumers include mask error correction (MEC), mask rule check (MRC), and other mask-data processing operations. The multi-scale shape processor provides extensible parameters to control the simplification and coordinate density. As the objective of optimization differs between the downstream consumers, the pre-processor needs to support multiple use-cases. MEC needs to obtain good placement of the vertices defining the curvilinear shapes. MRC and other operations will use different quality metrics. We will use the OASIS P49 Multigon data format to store the simplified results and analyze the benefits of the multi-scale processing system.

Upcoming generations of integrated circuits will use anamorphic optics in high NA EUV scanners which will require two or more stitched mask exposures to achieve the equivalent exposure area of previous-generation scanners. The patterning at a stitching boundary between two mask exposures will be affected by additional process variation sufficiently large that the allowed patterns targeted to be printed at a stitching boundary must be restricted relative to patterns printed at other (single exposure) regions on the wafer. Therefore, the physical design of the chip being patterned must be aware of the stitching region and the design tuned to be stitching friendly. In this paper we will first describe the fundamental patterning difficulties involved in high NA EUV stitching. We will evaluate the potential of multiple design and mask synthesis options for enabling stitch-friendly patterning in high NA EUV. We will also show how co-optimization of design and mask synthesis solutions can help ensure manufacturability of stitched patterns while protecting against extensive physical design changes with high NA lithography.