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Synopsys AMS SIG 2023 offered sessions that focused on latest advances in Synopsys solutions for analog and mixed-signal design, layout and simulation for robust AMS designs and achieve better results, faster!
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Available Presentations
A 3nm Custom SRAM Layout Efficiency Improvement using User Defined Devices (UDD)
Ramesh Halli, Jigar Patel - MediaTek
As technology shrinks custom layout development is getting complex and time consuming. Layout Designer develop layout using the foundry provided PCell, which doesn’t meet all foundry guideline. Hence the designers spend a lot of time for creating layout with the default PCells. With innovative way of User Defined Device (UDD) facilitate in Layout productivity enhancement by creating user required PCells in a graphical manner.
Synopsys Full Custom Flow for Analog SoC Design
Tushar Bhattacharya - AB Circuits and Research Labs
ABCRL is an Automotive Electronics start-up doing our first chip design for a non-functional-safety application.The application has Analog Front End sensing requirements and simple digital processing and data forwarding to a network processor. The SoC is being developed using Global Foundries 130BCD technology and will go into an MCM package with dies procured from third-party vendors. For this project, we used Synopsys Custom flow for the very first time. All analog simulations were done using PrimeSim HSPICE in the PrimeWave environment and Schematics and Layouts were developed in Custom Compiler. In this talk, we will share our experience as first-time users of Custom Compiler.
Effective Mixed Signal Verification Methodology for SerDes IP
Chirag Aggarwal - STMicroelectronics
SerDes IPs are quintessential for Mobile, IoT, High Performance Computing and many other high-speed applications. From verification perspective, because of the large size of the IP and sizable digital controller and the need to verify the IP in entirely, it’s important to have a robust mixed signal environment for complete validation of the IP. In this presentation, we will discuss about the challenges of SerDes verification and our verification methodology.
Enhancing Full Chip CCK_SOA COSIM Performance by Optimal Rule Selection Techniques
Hari Kiran Dawat, Somashekhar Puranmath, Varun Gutta - Micron Technology
Dynamic enable/disable of the asserts using the DUT signal, smart selection of relevant only rules from the entire CCK SOA rule set based on the functional mode of the simulation and netlist parsing to compare the transistor attributes with all the CCK rules set and to eliminate those instances which actually does not need transient check for a given rule. Making full chip static floating check feasible with the netlist contain non-synthesized digital blocks (which is the usual case with all the Initial Full chip netlists) and there by left shifting the Verification. To determine if the digital block is an empty subckt or not and then identify the output/inout ports of that digital block. Generate a dc force file for those output/input ports using the design intended values which will help to not only eliminate the huge false violations but also proceeds the check forward to identify issues inside the spice blocks. Employing this method also ensures same TB can be used for all types of netlists (fully synthesized or not), in case of fully synthesized It generate empty force files.