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ASIP 5G Wireless Seminar
Watch this virtual event on demand to learn more about the power of application-specific instruction-set processors (ASIPs) and ASIP Designer
Extending Processors into Flexible Accelerators for 5G using ASIP Designer
Case Studies in Wireless Signal Processing
The slow-down of Moore’s law and Dennard scaling triggered an increased awareness for application-specific instruction-set processors (ASIPs). These processors implement a specialized instruction-set architecture (ISA) tailored to the application domain, often starting from a baseline such as the RISC-V ISA. ASIPs can replace traditional fixed-function hardware accelerators, thereby introducing software-programmability in the acceleration domain, and thus more flexibility and agility in both the design process and the eventual product. By maintaining a RISC-V ISA baseline, compatibility with and reuse of existing processor ecosystem elements is facilitated.
Synopsys’ ASIP Designer is the industry-leading tool to design, implement, program and verify application-specific instruction-set processors. Starting from a single processor specification, designers immediately obtain an optimizing C/C++ compiler, cycle-accurate simulator and synthesizable hardware implementation of the ASIP. Using a unique compiler-in-the-loop™ and synthesis-in-the-loop™ methodology, the ISA and microarchitecture can be tuned quickly to the application domain.
This seminar introduces you to the ASIP Designer tool-suite. It features two case studies from popular application domains. The first case study by Lund University presents an application-specific vector processor for CNN based massive MIMO user terminal positioning. The ASIP contains a scalar RISC processor extended with a vector datapath and integrated accelerators. The second case study by Synopsys shows an accelerator for 5G NR channel equalization. A RISC baseline architecture is gradually extended into a highly parallel and specialized ASIP optimized for MMSE channel equalization using Cholesky Decomposition..
Agenda
9:00am - 9:30am CEST
An Introduction to Domain-Specific Processors, and ASIP Designer
Patrick Verbist, Product Marketing Manager, Synopsys Belgium
Falco Munsche, Technical Marketing Manager, Synopsys Germany
Domain-specific processors (also referred to as Application-specific processors, ASIP) combine hardware specialization with flexibility through software programmability. This session will introduce the concept of ASIPs, and will provide an overview of Synopsys' ASIP Designer tool suite.
9:30am - 10:00 am CEST
Case study: An Application Specific Vector Processor for CNN-based Massive MIMO Positioning
Mohammad Attari, PhD student in the Digital ASIC Research Group in the Electrical and Information Technology (EIT) Department, Lund University
As 5G-capable networks and devices gradually roll into the market, they bring with them a host of exciting applications. One example use-case is terminal positioning, and in this work we set out to create an application specific instruction set processor (ASIP) implementation to enable user positioning in a wireless system by means of deep convolutional neural networks (CNN). The positioning is based on the fingerprinting method using massive multiple-input multiple-output (MIMO) technology, and utilizes the wireless channel state information (CSI). The ASIP is designed to combine flexibility with implementation efficiency, and is equipped with vector processing capabilities employing a single instruction multiple data (SIMD) scheme, and additionally has a very large instruction word (VLIW) architecture to further exploit instruction-level parallelism. Due to the sheer volume of computational requirements imposed by CNN processing, an accelerator-assisted design is well-suited to the task at hand. As a result, a configurable 2D array of processing engines (PE) is integrated into the processor, in a tightly coupled manner, to accelerate the CNN operation. Synthesis results will be demonstrated using the GF-22nm FD-SOI technology.
10:00am - 11:00 am CEST
Case study: 5G NR MMSE Channel Equalization using Cholesky Decomposition (includes tool demonstrations)
Falco Munsche, Technical Marketing Manager, Synopsys Germany
5G New Radio (NR) channel equalization algorithms are very demanding in respect of processing power (several TMAC/s), requiring a huge number of complex-number MAC operations in combination with high memory bandwidth and quite irregular memory access patterns. In this ASIP design, customized instructions and datapaths were added to a baseline RISC design in a stepwise approach. Multiple implementation solutions and their performance-versus-cost tradeoffs were explored with fast turnaround, using the compiler-in-the-loop™ and synthesis-in-the-loop™ optimization flows of ASIP Designer. These flows allow for iterative co-optimization of the application code and the ASIP architecture while verifying their correctness and performance at each step. The resulting design is a highly specialized ASIP featuring custom instructions, data level parallelism (SIMD), instruction level parallelism (ILP), and multicore context, which optimally balances the datapath with the memory bandwidth, and the SIMD size with the number of cores.
