Cloud native EDA tools & pre-optimized hardware platforms
Date & Time: Tuesday, February 25 | 11:10 – 11:50 AM
Room: Grand Ballroom 220C
Recent innovations in artificial intelligence (AI) have already led to startling changes in how humans operate in their daily lives. In this talk, I will attempt to forecast not only the technological innovations that will be developed and adopted for the most advanced process nodes in semiconductor manufacturing, but also what the role of the human engineer is likely to be in a rapidly changing world where generative AI is likely to be pervasive. While forecasting the future is notoriously inaccurate, I will try to not be shy about putting forward provocative, stimulating, and hopefully thoughtful ideas in a variety of areas. I will discuss how we can expect various AI agents to be trained within our specialized domain, how to deal with knowledge that is messy and poorly organized, and how AI and human engineers can co-exist in our field. Ultimately, what is the role of the human engineer in the future of pervasive AI, and what will such a co-existence of human and AI look like?
EUV NTD resist modeling and mechanisms of deformation
11:30 AM - 11:50 AM PST | Grand Ballroom 220A
2:00 PM - 2:20 PM PST | Grand Ballroom 220C
4:50 PM - 5:10 PM PST | Grand Ballroom 220C
Full field stitching-aware high-NA EUV OPC/RET flow
9:40 AM - 10:00 AM PST | Grand Ballroom 220A
Exploring block-level PPA improvements using SuperVia: Implementation and analysis in a 2nm process (Invited Paper)
11:50 AM - 12:10 PM PST | Grand Ballroom 220C
An innovative stitching solution for multi-patterning compliant routing metal layers beyond 2nm
3:50 PM - 4:10 PM PST | Grand Ballroom 220C
Metaatom choice considering process variation
5:10 PM - 5:30 PM PST | Grand Ballroom 220C
OPC by matrix solver with rigorous model
5:30 PM - 7:00 PM PST | Hall 2
The exploration of curvilinear mask manufacturability and wafer printability
5:30 PM - 7:00 PM PST | Hall 2
8:20 AM - 8:40 AM PST | Grand Ballroom 220C
Automated identification of repeated chip layout patterns
10:00 AM - 10:20 AM PST | Grand Ballroom 220C