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Why Attend?
Join us for an exclusive and exciting opportunity to participate in an interactive forum where you'll discover the latest updates to Synopsys' cutting-edge mask synthesis products. You'll gain invaluable insights into the current challenges and solutions for advanced imaging from industry leaders who specialize in EUV, rigorous simulation, compact modeling, verification, ILT technologies and mask data prep. Don't miss out on this chance to hear from the best in the business! Register now to secure your spot at this must-attend virtual event.
Agenda at a Glance
- Welcome Introduction | Kostas Adam, VP Engineering, Synopsys
- Advances in Computational Lithography Solutions for High NA EUV Manufacturing
Michael Lam, Sr. Director, R&D Engineering, Synopsys
- Curvilinear Full Chip ILT and OPC for low-k1 DUV and EUV Lithography
Thuc Dam, Director, Product Engineering, Synopsys
- Curve Mask Data Preparation/Verification for High Fidelity Mask Manufacturing
Kokoro Kato, Sr. Dir, R&D Engineering, Synopsys
- Accelerating Litho Pathfinding Through Simulation for Memory/Logic/Display
Wolfgang Demmerle, Product Marketing Manager, Synopsys
- AI Applications, Benefits, and Future Opportunities
WooJoo Sim, Sr. Manager, R&D Engineering, Synopsys
Watch Now
Detailed Agenda
Kostas Adam
VP Engineering
Synopsys
Welcome Introduction
Wednesday, September 11, 2024
8:00 a.m. CEST | 2:00 p.m. CST | 3:00 p.m. JST
Advances in Computational Lithography Solutions for High NA EUV Manufacturing
Wednesday, September 11, 2024
8:15 a.m. CEST | 2:15 p.m. CST | 3:15 p.m. JST
The path to a viable EUV manufacturing solution has been long and difficult, requiring substantial innovation by the lithography community over multiple decades. The fruits of that labor are upon the industry, with EUV becoming a critical, enabling step in modern semiconductor manufacturing processes. A new set of challenges present themselves to the industry as we look to achieve even higher resolution with ‘high-NA’ EUV tools. Fortunately, computational lithography solutions for high-NA tools exist, and can accelerate learning and understanding prior to widespread access to physical machines. This paper will discuss the modifications to computational lithography modeling and its flows, needed to enable manufacturing with high-NA EUV tools.
Michael Lam
Sr. Director, R&D Engineering
Synopsys
Thuc Dam
Director, Product Engineering
Synopsys
Curvilinear Full Chip ILT and OPC for low-k1 DUV and EUV Lithography
Wednesday, September 11, 2024
8:45 a.m. CEST | 2:45 p.m. CST | 3:45 p.m. JST
Advancements in computational lithography and mask writing are ushering in a new era of high-fidelity curve masks in semiconductor lithography. As mask manufacturing constraints diminish, the emphasis is now on maximizing the capabilities of our process correction tools. The complexity of curvilinear mask and target correction presents a unique challenge, with a myriad of quality determinants, cost considerations, and solutions needed to meet diverse requirements across various layers, devices, and lithographic applications.
This talk will delve into the spectrum of advancements in producing highest quality curvilinear masks facilitated by Inverse Lithography Technology (ILT), the integration of curve-based ILT and Optical Proximity Correction (OPC), and the enablement of full-chip curve ILT flows. These solutions, capable of meeting the quality and computational cost requirements, are key enablers for advanced lithography. The presentation will also highlight the latest progress in data volume reduction, a key aspect of the curvilinear mask ecosystem. Leveraging co-optimization and hybrid flows with ILT to tackle computation times and to enable full-chip quality will bring a new chapter in semiconductor manufacturing.
Curve Mask Data Preparation/Verification for High Fidelity Mask Manufacturing
Wednesday, September 11, 2024
9:15 a.m. CEST | 3:15 p.m. CST | 4:15 p.m. JST
Leading-edge semiconductor manufacturers have started using masks with curvilinear patterns for better yield enabled by ILT (Inverse Lithography Technology). In addition, the mask industry is deploying Real Curve masks such as Bezier curves for data volume reduction as defined Semi-P49. This presentation will explain the background of these technologies and discuss the impact on the data preparation and verification flow.
Kokoro Kato
Sr. Dir, R&D Engineering
Synopsys
Wolfgang Demmerle
Product Marketing Manager
Synopsys
Accelerating Litho Pathfinding Through Simulation for Memory/Logic/Display
Wednesday, September 11, 2024
9:45 a.m. CEST | 3:45 p.m. CST | 4:45 p.m. JST
Rigorous simulations represent an invaluable tool for exploring patterning options and assessing their lithographic performance – at any semiconductor device type and technology. Physics-based models help to predict the impact of process variations on the printed results on silicon wafers or glass substrates without running costly experiments.
A key contributor to successful simulations is the precise characterization of lithographic setup conditions. While exposure tool properties such as illumination and projection parameters are well described, mask absorber and wafer feature attributes are determined through electron beam metrology tools such as CD-SEMs.
In this presentation, we demonstrate the efficient use of contours extracted from SEM images to characterize mask or wafer features with respect to placement, pattern fidelity, and uniformity. Defects can be are automatically detected and categorized, and severity can be easily assessed by simulation.
The interaction between substrate and photoresist system as well the formation of 3D resist profiles is described by a multitude of different mechanisms, where metrology data is essential to determine the appropriate model parameters. We will use a wide range of examples to demonstrate the power of rigorous modeling, from resist reflow (i-line), via DUV sub-80nm pitch resolution challenges (ArF immersion), to metal oxide resist / underlayer systems (high NA EUV).
AI Applications, Benefits, and Future Opportunities
Wednesday, September 11, 2024
10:15 a.m. CEST | 4:15 p.m. CST | 5:15 p.m. JST
Artificial intelligence (AI) has been spreading rapidly across industries in recent years. Its influence in the semiconductor industry is also increasing, replacing many technical steps in areas from design to manufacturing with improved accuracy and performance. One recent trend in the era of AI is the saturation of AI models and the increasing importance of data. Over the past few years, superb AI models have been developed and their impact has grown, but on the other hand, new models have appeared less and less frequently. Now the focus is shifting from the model to the data, and the amount of data and its proper representation are becoming more and more important. What differentiates Synopsys AI from competitors is in this perspective. First, we have large data from different areas including design, TCAD, and lithography, which are closely related to each other in terms of optimizing their costs and runtime. Second, the physics of each domain is reflected to the representation of the data with proper featurization. As a result, the AI models trained with the data will become more robust in both training and inference. Furthermore, this aspect will accelerate the development of a large generative AI model that spans both design and lithography space of the large data, which can be applied to any specific cases with or without fine tuning. Finally, when this large generative model is combined with other kinds of AI technologies that are being developed in Synopsys, which include optimization AI and generative AI for language data, more significant enhancements will be attainable in terms of productivity.
WooJoo Sim
Sr. Manager, R&D Engineering
Synopsys
Meet The Presenters
Kostas Adam
VP Engineering
Synopsys
Kostas Adam leads Synopsys R&D and Product Engineering for the Mask Solutions group. Prior to that, he was with Siemens EDA (known as Mentor Graphics until the 2017 acquisition by Siemens) for more than 20 years. He has worked in the Calibre OPC product line, in roles ranging in the early years from individual contributor to most recently the VP of engineering for all Mask Synthesis products of Calibre. Kostas has a PhD degree in EECS from UC Berkeley.
Michael Lam
Sr. Director, R&D Engineering
Synopsys
Michael performed his graduate studies in computational lithography at UC Berkeley where he focused on fast 3D mask modeling projects, including buried defect simulations of EUV mask blanks. He spent two summers studying phase defect printability as an intern at Intel, as well as one summer co-founding CommandCAD, a DFM startup working on image-based 2D design rule checking that was eventually acquired by Cadence. He received his PhD in Applied Science and Technology from UC Berkeley in 2005 before joining Mentor Graphics as a modeling software engineer. Over 17 years at Mentor, Michael was involved in all aspects of computational lithography modeling, ending his time as Director of Modeling, SMO, ILT, and GPU Simulation. He joined Synopsys in May of last year as Director of R&D for Computational Lithography Modeling.
Thuc Dam
Director, Product Engineering
Synopsys
Thuc Dam holds a PhD in applied organic chemistry from UTD. He has worked in semiconductor field for 23 years with 30+ publications and 2 patents, and has previously been employed in technical and managerial roles at Intel and Luminescent Inc. His innovations in mask process development, ILT, SMO, and DRE have contributed extensively to the computational lithography domain. He is growing his experience in DTCO, AR/VR and EUV. He is currently a Sr. Product Engineering Manager for the ILT and SMO groups at Synopsys.
Kokoro Kato
Sr. Dir, R&D Engineering
Synopsys
Dr. Kato received his PhD from Tokyo University specializing in Mask Rule Checking (MRC) using massive distributed parallel processing. His career spans over three decades in the field of Electronic Design Automation (EDA). In 1992 he started his career with the development of the layout editor SX9000 at Seiko. His career trajectory then shifted towards mask-related software, where he and his team achieved significant commercial success with SmartMRC, a robust MRC tool. This accomplishment led to the acquisition of his team by Synopsys in 2015. Dr. Kato has held significant leadership roles within the industry. From 2011 to 2014, he served as the chairperson of the Photomask Japan (PMJ) technical committee. He continues to contribute to the field in his current role as the chairperson of the PMJ steering committee.
Wolfgang Demmerle
Product Marketing Manager
Synopsys
Wolfgang is Product Marketing Manager for computational lithography simulation solutions at Synopsys. He joined the company in 2006 through the acquisition of Sigma-C. Wolfgang has more than 25 years of experience in the semiconductor industry. He obtained broad lithography know-how through engineering positions at Nikon Precision and ASML. Wolfgang received his PhD in Semiconductor Physics from the Technical University of Munich (Germany).
WooJoo Sim
Sr. Manager, R&D Engineering
Synopsys
WooJoo is a Senior Manager of R&D at Synopsys, specializing in AI solutions for lithography and Optical Proximity Correction (OPC). His journey began with a Ph.D. at POSTECH, studying string theory. He then worked at Samsung Electronics on OPC, inspired by AlphaGo to delve into artificial intelligence. As a visiting scholar at the University of Michigan, he studied deep learning OPC and design optimization. He led the development of Samsung's in-house OPC software, applying deep learning techniques to enhance performance. WooJoo also worked at Standigm, an AI drug discovery company, before returning to the OPC field at Synopsys, aiming to expand its applications.